1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to an integrable data/clock recovery unit (DCRU) including a recovery phase-lock-loop (PLL) for capturing and processing serial data streams.
2. Description of the Prior Art
A common data encoding protocol used in serial, single channel, digital communication is comprised of the interleaving of digital data with write time-base (clock) pulses. The interval between the clock pulses is defined as a "bit cell", and the data bit usually resides in the middle of the bit cell. Repeated bit cells whose data contents are either all logic zeros or all logic ones, commonly referred to as "sync fields", are buried in the pulse streams to provide an opportunity for the recovery circuits to periodically synchronize.
Digital cassettes, digital magnetic tapes, floppy and hard disk and radio telemetry are all examples of systems which use the above described transmission protocol. Tapes and disks represent special cases which involve moving magnetic media, and which introduce significant time and phase distortion due to the mechanical nature of their design; e.g. the speed of a floppy disk can vary as much as plus or minus 10%. Such distortions in the data time-base impose severe performance burdens on data recovery and separation circuitry, especially in view of industry demands for increased data densities and data rates.
The phase-lock-loop (PLL) technique has proven to be the most reliable technique for data/clock recovery and separation. This approach utilizes a phase comparator, filter and voltage controlled oscillator (VCO) coupled in a feedback loop configuration in such a way that the VCO locks onto the phase and/or frequency of an incoming periodic wave form. Advances in semiconductor integrated circuit technology now permit such circuits to be integrated; however, known phase-lock-loops require circuits of moderate complexity and component count. Not only is performance often compromised in order to maintain the component counts at reasonable levels, but efforts thus far to produce integrated circuit PLLs have represented poor marriages between integrated analog and digital electronics resulting in loops of limited performance.
Several non-integrated techniques have been employed to improve loop performance by reducing loop phase jitter caused by loop electrical noise. A first approach utilizes torroids in the wires to the power supply leads of the loop filter and VCO. This, however, does not completely solve the problem caused by ground noise which itself will result in loop jitter. A second approach utilizes separate power supplies to drive the loop filter and VCO; a solution which is both costly and cumbersome. Prior art approaches to data recovery rely heavily on software techniques to reduce soft error rate. That is, a great deal of reliance is placed on error correcting codes and software routines to detect and correct soft errors. Additionally, prior art system performance has been limited in that phase tracking is generally dependent on input data format; i.e. irregular spaced data in certain designs cause loop tracking difficulties.